1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to architecture and organization of a dynamic random-access memory array and associated supporting circuitry for its high-speed reading and writing.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
In many integrated circuit devices, internal circuitry frequently operates using a single positive power supply voltage, VDD, and the reference voltage VSS (i.e., "ground"). The bit lines of a dynamic memory array are frequently equilibrated to a voltage near one-half of the power supply voltage (i.e., VDD/2 equilibration), and bit line sense amplifiers are implemented using a full CMOS cross-coupled latch. Such a CMOS latch includes a cross-coupled N-channel pair of transistors (i.e., the NMOS sense amplifier) and the cross-coupled P-channel pair of transistors (i.e., the PMOS sense amplifier). To sense the signal on a pair of bit lines, both the NMOS sense amplifier and the PMOS sense amplifier are usually enabled at substantially the same time. The NMOS sense amplifier drives the bit line having a lower voltage toward VSS, while the PMOS sense amplifier drives the bit line having a higher voltage toward VDD. After the lower bit line substantially reaches VSS and the higher bit line substantially reaches VDD, both the NMOS sense amplifier and the PMOS sense amplifier are usually disabled (along with the selected word line).
It usually takes longer to sense and restore a high-going bit line due to the inherently slower PMOS transistors compared to NMOS, as well as the greater difficulty in writing a high voltage into an NMOS array due to the significant decrease in the gate-to-source voltage at high cell (source) voltage and the apparent increase of threshold voltage resulting from increased source-to-body back-bias voltage (i.e., body effect) of memory cell access transistors and array select transistors. Moreover, as the VDD voltage has decreased in recent years to an ever lower magnitude, there is even less "turn-on" voltage (i.e., gate-to-source voltage minus the threshold voltage) for the PMOS transistors within the PMOS sense amplifier. The time required for the PMOS sense and restore function to drive the high-going bit line to a predetermined voltage is a significant portion of an active cycle. Further improvements in dynamic memory array performance, including PMOS sense and restore, are desired.